Switching Activity Minimization in Combinational Logic Design
نویسندگان
چکیده
Abstract: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal optimal solution obtained from k-map to reduce its switching activity. More than 10% reduction in switching activity has been observed using our method. The final solution gives a good trade off between cost and power consumption.
منابع مشابه
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each gate. A powerful combinational logic optimization method using k-map is presented here that is based on disjoint implicants (implicates) of a function. More than 10% reduction in switching activity has been obtained wit...
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